ICS8343-01 Datasheet, PDF (2/10 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8343-01
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 3
4, 5
V_DD1
Q3, Q4
Power
Output
Q0 thru Q7 output supply pins.
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
6, 7, 8,
17, 18, 19
GND
Power
Power supply ground.
9, 10, 11 Q5, Q6, Q7 Output
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
12
CLK
Input Pulldown LVCMOS/LVTTL clock input / 5V tolerant.
13
V
DD
14, 15, 16 Q8, Q9, Q10
Power
Output
Core supply pin.
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
20, 21
Q11, Q12
Output
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
22, 23, 24
V_DD2
Power
25, 26, 27 Q13, Q14, Q15 Output
Q8 thru Q15 output supply pins.
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
28
OE2
Input
Pullup
Output enable. When low forces outputs Q8 thru Q15 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
29
OE1
Input
Pullup
Output enable. When low forces outputs Q0 thru Q7 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
30, 31, 32 Q0, Q1, Q2 Output
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
C_PD
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
R_PULLUP
R_PULLDOWN
R_OUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
V_DD, V_DD1, V_DD2 = 3.465V
V_DD1, V_DD2 = 2.63V
V_DD, V_DD1, V_DD2 = 3.3V
Minimum
5
Typical
4
11
9
51
51
7
Maximum
12
Units
pF
pF
pF
KΩ
KΩ
Ω
TABLE 3. FUNCTION TABLE
Inputs
Outputs
OE1
OE2
Q0:Q7
Q8:Q15
0
0
HiZ
HiZ
1
0
Active
HiZ
0
1
HiZ
Active
1
1
Active
Active
NOTE: OE1 and OE2 are 5V tolerant.
8343AY-01
www.icst.com/products/hiperclocks.html
2
REV. B SEPTEMBER 16, 2004