ICS83054I-01 Datasheet, PDF (4/12 Pages) Integrated Circuit Systems – 4-BIT, 2 : 1, SINGLE-ENDED MULTIPLEXER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83054I-01
4-BIT, 2:1,
SINGLE-ENDED MULTIPLEXER
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK0, CLK1
V_DD = 3.3V ± 5%
2
V_IH
Input High Voltage
OE,
V_DD = 2.5V ± 5%
1.7
V_DD = 3.3V ± 5%
2
SEL0:SEL3
V_DD = 2.5V ± 5%
1.7
V_DD + 0.3
V
V_DD + 0.3
V
V_DD + 0.3
V
V_DD + 0.3
V
CLK0, CLK1
V_DD = 3.3V ± 5%
-0.3
V_IL
Input Low Voltage
OE,
V_DD = 2.5V ± 5%
-0.3
V_DD = 3.3V ± 5%
-0.3
SEL0:SEL3
V_DD = 2.5V ± 5%
-0.3
1.3
V
0.7
V
1.3
V
0.7
V
I_IH
CLK0, CLK1,
Input High Current ^SEL0:SEL3
V_DD = 3.3V or 2.5V ± 5%
OE
V_DD = 3.3V or 2.5V ± 5%
150
µA
5
µA
I_IL
CLK0, CLK1,
Input Low Current ^SEL0:SEL3
V_DD = 3.3V or 2.5V ± 5%
-5
µA
OE
V = 3.3V or 2.5V ± 5%
-150
µA
DD
V_DDO = 3.3V ± 5%; NOTE 1
2.6
V
V_OH
Output HighVoltage
V_DDO = 2.5V ± 5%; NOTE 1
1.8
V
V_DDO = 1.8V ± 0.2V; NOTE 1 V_DD - 0.3
V
V_DDO = 3.3V ± 5%; NOTE 1
0.5
V
V
Output Low Voltage
OL
V = 2.5V ± 5%; NOTE 1
DDO
0.45
V
V_DDO = 1.8V ± 0.2V; NOTE 1
0.35
V
NOTE 1: Outputs terminated with 50Ω to V_DDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE
5A.
AC
CHARACTERISTICS,
V
DD
=
V
DDO
=
3.3V
±
5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
tp_LH
Propagation Delay, Low to High;
NOTE 1
tp_HL
Propagation Delay, High to Low;
NOTE 1
250
2.5
2.65
tsk(i) Input Skew; NOTE 5
45
tsk(pp) Part-to-Part Skew; NOTE 2, 5
TBD
Buffer Additive Phase Jitter, RMS;
tjit
refer to Additive Phase Jitter section,
NOTE 4
Integration Range:
12KHz - 20MHz
0.07
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
535
50
t_EN
Output Enable Time; NOTE 3
5
t_DIS
Output Disable Time; NOTE 3
5
MUX_ISOL MUX Isolation
@100MHz
45
NOTE 1A: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ns
ps
ps
ps
ps
%
ns
ns
dB
83054AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
4