ICS5250708 Datasheet, PDF (4/9 Pages) Integrated Circuit Systems – LVCMOS User Configurable Clock

PRELIMINARY INFORMATION
ICS525-07/08
LVCMOS User Configurable Clock
Output Frequency and Output Divider Table (ICS525-07)
S2 S1 S0 CLK Output
Pin 5 Pin 4 Pin 3 Divider
0
0
0
12
0
0
1
2
0
1
0
16
0
1
1
4
1
0
0
5
1
0
1
7
1
1
0
1
1
1
1
3
Output Frequency Range (MHz)
VDD = 2.5 V
VDD = 1.8 V
Min
Max
Min
Max
8.3
20.8
8.3
20.8
50
125
50
125
6.25
15.63
6.25
15.63
25
62.5
25
62.5
20
50
20
50
14.3
35.7
14.3
35.7
100
250
100
250
33.3
83.33
33.3
83.33
Output Frequency and Output Divider Table (ICS525-08)
S3 S2 S1 S0 CLK Output
Pin 2 Pin 5 Pin 4 Pin 3 Divider
0
0
0
0
2
0
0
0
1
3
0
0
1
0
4
0
0
1
1
5
0
1
0
0
7
0
1
0
1
8
0
1
1
0
9
0
1
1
1
10
1
0
0
0
11
1
0
0
1
13
1
0
1
0
14
1
0
1
1
15
1
1
0
0
17
1
1
0
1
19
1
1
1
0
48
1
1
1
1
128
Output Frequency Range (MHz)
VDD = 2.5 V
VDD = 1.8 V
Min
Max
Min
Max
23.9
200
23.9
200
15.9
200
15.9
200
11.9
200
11.9
200
9.5
158.4
9.5
158.4
6.8
113.1
6.8
113.1
6.0
99.0
6.0
99.0
5.3
88.0
5.3
88.0
4.8
79.2
4.8
79.2
4.3
72.0
4.3
72.0
3.7
60.9
3.7
60.9
3.4
56.6
3.4
56.6
3.2
52.8
3.2
52.8
2.8
46.6
2.8
46.6
2.5
41.7
2.5
41.7
1.0
16.5
1.0
16.5
0.4
6.2
0.4
6.2
MDS 525-07/08 A
4
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com