ICS93705 Datasheet, PDF(3/7 Page) Integrated Circuit Systems – DDR Phase Lock Loop Zero Delay Clock Buffer

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ICS93705 Datasheet, PDF (3/7 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Zero Delay Clock Buffer

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ICS9370 5

Byte 2: Reserved

(1= enable, 0 = disable)

BIT PIN# PWD

DESCRIPTION

Bit 7 -

1 Reserved

Bit 6 -

1 Reserved

Bit 5 -

1 Reserved

Bit 4 -

1 Reserved

Bit 3 -

1 Reserved

Bit 2 -

1 Reserved

Bit 1 -

1 Reserved

Bit 0 -

1 Reserved

Byte 4: Reserved

(1= enable, 0 = disable)

BIT PIN# PWD

DESCRIPTION

Bit 7 -

1 Reserved

Bit 6 -

1 Reserved

Bit 5 -

1 Reserved

Bit 4 -

1 Reserved

Bit 3 -

1 Reserved

Bit 2 -

1 Reserved

Bit 1 -

1 Reserved

Bit 0 -

1 Reserved

Byte 3: Reserved

(1= enable, 0 = disable)

BIT PIN# PWD

DESCRIPTION

Bit 7 -

1 Reserved

Bit 6 -

1 Reserved

Bit 5 -

1 Reserved

Bit 4 -

1 Reserved

Bit 3 -

1 Reserved

Bit 2 -

1 Reserved

Bit 1 -

1 Reserved

Bit 0 -

1 Reserved

Byte 5: Reserved

(1= enable, 0 = disable)

BIT PIN# PWD

DESCRIPTION

Bit7 3,2

1 CLK0 (T&C)

Bit6

Bit5 10, 9 1 CLK2 (T&C)

Bit4 20, 19 1 CLK3 (T&C)

Bit3 22, 23 1 CLK4 (T&C)

Bit2 27, 26 1 CLK9 (T&C)

Bit1 -

1 Reserved

Bit0

1 Reserved

Byte 6: Reserved

(1= enable, 0 = disable)

BIT PIN# PWD

DESCRIPTION

Bit7 -

0 Reserved (Note)

Bit6 -

0 Reserved (Note)

Bit5 -

0 Reserved (Note)

Bit4 29, 30 1 CLK8 (T&C)

Bit3 39, 40 1 CLK7 (T&C)

Bit2 44, 43 1 CLK6 (T&C)

Bit1 46, 47 1 CLK5 (T&C)

Bit0 -

1 Reserved

Note: Donât write into these registers (7:5), writing into

these registers can cause malfunction.

0418Câ08/08 /02

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