ICS93705 Datasheet, PDF (1/7 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Zero Delay Clock Buffer

Integrated
Circuit
Systems, Inc.
ICS9370 5
DDR Phase Lock Loop Zero Delay Clock Buffer
Recommended Application:
DDR Zero Delay Clock Buffer
Product Description/Features:
• Low skew, low jitter PLL clock driver
• I²C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• 3.3V tolerant CLK_INT input
Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (66MHz):<120ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 450ps - 950ps
• DUTY CYCLE: 49% - 51%
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
SCLK
CLK_INT
N/C
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1
48
GND
2
47
CLKC5
3
46
CLKT5
4
45
VDD
5
44
CLKT6
6
43
CLKC6
7
42
GND
8
41
GND
9
40
CLKC7
10
39
CLKT7
11
38
VDD
12
37
SDATA
13
36
N/C
14
35
FB_INT
15
34
VDD
16
33
FB_OUTT
17
32
N/C
18
31
GND
19
30
CLKC8
20
29
CLKT8
21
28
VDD
22
27
CLKT9
23
26
CLKC9
24
25
GND
48-Pin SSOP
Block Diagram
SCLK
SDATA
Control
Logic
FB_INT
PLL
CLK_INT
FB_OUTT
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
Functionality
INPUTS
OUTPUTS
AVDD CLK_INT CLKT CLKC FB_OUTT
2.5V
(nom)
L
LH
L
2.5V
(nom)
H
HL
H
2.5V
(nom)
<20MHz⁽¹⁾
Z
Z
Z
GND
L
LH
L
GND
H
HL
H
PLL State
on
on
off
Bypassed/off
Bypassed/off
0418C—08/08/02