ICS932S200 Datasheet, PDF (3/12 Pages) Integrated Circuit Systems – Frequency Timing Generator for Dual Server/Workstation Systems

ICS932S200
Frequency Select:
SEL
133/100#
SEL1
SEL0
0
00
0
0
1
CPU
MHz
Hi-Z
N/A
3V66
MHz
Hi-Z
N/A
PCI
MHz
Hi-Z
N/A
48
MHz
Hi-Z
N/A
0
1 0 100 66.6 33.3 Hi-Z
0
1
1 100 66.6 33.3 48.0
1
0 0 TCLK/2 TCLK/4 TCLK/8 TCLK/2
1
0
1 N/A N/A N/A N/A
1
1 0 133 66.6 33.3 Hi-Z
1
1
1 133 66.6 33.3 48.0
REF
MHz
Hi-Z
N/A
IOAPIC
MHz
Hi-Z
N/A
14.318 16.67
14.318 16.67
TCLK TCLK/16
N/A N/A
14.318 16.67
14.318 16.67
Comments
Tri-state
Reserved
48MHz PLL
disabled
Test mode (1)
Reserved
Note:
1. TCLK is a test clock driven on the x1 input during test mode.
ICS932S200 Power Management Features:
CPU_STOP#
X
PD# PCI_STOP# CPUCLK IOAPIC 3V66
0
X
LOW LOW LOW
PCI
PCI_F
REF.
48MHz
Osc
LOW LOW LOW OFF
VCOs
OFF
0
1
0
LOW
ON LOW LOW ON
ON
ON
ON
0
1
1
LOW
ON LOW ON
ON
ON
ON
ON
1
1
0
ON
ON
ON LOW ON ON
ON
ON
1
1
1
ON
ON
ON
ON
ON ON
ON
ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
4. All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW.
5. IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions
except PD# = LOW
0427C—07/03/02
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