ICS9150-02 Datasheet, PDF (3/8 Pages) Integrated Circuit Systems – Pentium Pro and SDRAM Frequency Generator

ICS9150- 02
Preliminary Product Preview
Technical Pin Function Descriptions
VDD(1,2,3,4)
This is the power supply to the internal core logic of the device as well
as the clock output buffers for REF(0:1), PCICLK, 48MHz (0:1)
and SDRAM(0:7).
This pin operates at 3.3V volts. Clocks from the listed buffers that it
supplies will have a voltage swing from Ground to this level. For the
actual guaranteed high and low voltage levels for the Clocks, please
consult the DC parameter table in this data sheet.
VDDL1,2
This is the power supplies for the CPUCLK and IOAPCI output
buffers. The voltage level for these outputs may be 2.5 or 3.3volts.
Clocks from the buffers that each supplies will have a voltage swing
from Ground to this level. For the actual Guaranteed high and low
voltage levels of these Clocks, please consult the DC parameter
table in this Data Sheet.
GND
This is the power supply ground (common or negative) return pin for
the internal core logic and all the output buffers.
X1
This input pin serves one of two functions. When the device is used
with a Crystal, X1 acts as the input pin for the reference signal that
comes from the discrete crystal. When the device is driven by an
external clock signal, X1 is the device input pin for that reference
clock. This pin also implements an internal Crystal loading capacitor
that is connected to ground. With a nominal value of 33pF no
external load cap is needed for a C_L=17 to 18pF crystal.
X2
This Output pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is an
output signal that drives (or excites) the discrete Crystal. The X2 pin
will also implement an internal Crystal loading capacitor nominally
33pF.
CPUCLK (0:4)
These Output pins are the Clock Outputs that drive processor and
other CPU related circuitry that requires clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of these
Clocks are controlled by theVoltage level applied to theVDDL2 pin
of the device. See the FunctionalityTable for a list of the specific
frequencies that are available for these Clocks and the selection
codes to produce them.
SDRAM(0:12)
These Output Clocks are use to drive Dynamic RAM’s and are low
skew copies of the CPU Clocks. The voltage swing of the
SDRAM’s output is controlled by the supply voltage that is applied
to VDD3 of the device, operates at 3.3 volts.
IOAPIC (0:1)
These Outputs are fixed frequency Output Clocks that run at the
Reference Input (typically 14.31818MHz) . Its voltage level swing
is controlled by VDDL1 and may operate at 2.5 or 3.3volts.
REF (0:1)
The REF Output is a fixed frequency Clock that runs at the same
frequency as the Input Reference Clock X1 or the Crystal (typically
14.31818MHz) attached across X1 and X2.
PCICLK_F
This Output is equal to PCICLK(0:5).
PCICLK (0:5)
These Output Clocks generate all the PCI timing requirements for a
Pentium/Pro based system. They conform to the current PCI
specification.They run at 1/2 CPU frequency.
FS0
This Input pin controls the frequency of the Clocks at the CPU,
PCICLK and SDRAM output pins. If a logic “1” value is present on
this pin, the 66.6 MHz Clock will be selected. If a logic “0” is used,
the 60MHz frequency will be selected.
I²C
The SDATA and SCLOCK Inputs are use to program the device.
The clock generator is a slave-receiver device in the I²C protocol.
It will allow read-back of the registers. See configuration map for
register functions. The I²C specification in Philips I²C Peripherals
Data Handbook (1996) should be followed.
48MHz
This is a fixed frequency clock that is typically used to drive Super
I/O peripheral device needs and USB.
OE
Output Enable tristates the outputs when held low. This pin will
override the I²C Byte 0 function, so that the outputs will be tristated
when the OE is low regardless of the I²C defined function. When OE
is high, the I² C function is in active control.
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