ICS9150-02 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – Pentium Pro and SDRAM Frequency Generator

ICS9150- 02
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
2, 3
4, 10, 17, 23, 31,
34, 40, 47, 53
5
PIN NAME
REF (0:1)
GND
X1
6
X2
8
9, 11, 12, 13
14, 16
18, 19
21
27
28
29
30
1, 7, 15, 20, 26,
37, 43
50, 56
22, 24, 25, 32, 33,
35, 36, 38, 39, 41,
42, 44, 45
54, 55
46, 48, 49, 51, 52
PCICLK_F
PCICLK (0:5)
48MHz
N/C
SDATA
SCLK
OE
SEL 66/60#
VDD2, VDD1,
VDD3, VDD4
VDDL2, VDDL1
SDRAM (0:12)
IOAPIC (1:0)
CPUCLK (0:4)
TYPE
DESCRIPTION
OUT 14.318 MHz reference clock outputs.
PWR Ground.
IN
OUT
OUT
14.318MHz input. Has internal load cap,(33pF).
Crystal output. Has internal load cap (33pF) and feedback
resistor to X1
Free running BUS clock.
OUT BUS clock outputs.
OUT
-
IN
IN
IN
IN
48MHz clock outputs
Pins are not internally connected.
Serial data in for serial config port.
Clock input for serial config port.
Logic input for output enable, tristates all outputs when low.
Selects 60MHz or 66MHz for SDRAM and CPU.
PWR Nominal 3.3V power supply. See power groups for function.
PWR CPU and IOAPIC clock buffer power supply (2.5 - VDD)
OUT SDRAM clocks (60/66.6MHz)
OUT IOAPIC clock output. (14.31818 MHz) Powered by VDDL1
OUT CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:12), Supply for PLL core
VDD4 = 48 MHz
VDDL1 = IOAPIC (0:1)
VDDL2 = CPUCLK (0:4)
2