ICS85214I Datasheet, PDF (3/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nCLK_EN
Q0:Q4
nQ0:nQ4
0
Enabled
Enabled
1
Disabled; LOW
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 inputs as described in Table 3B.
nCLK0
CLK0
Disabled
Enabled
nCLK_EN
nQ0:nQ4
Q0:Q4
FIGURE 1. nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
CLK_SEL
Inputs
CLK0
nCLK0
Outputs
CLK1 Q0:Q4 nQ0:nQ4
Input to Output Mode
Polarity
0
0
1
X
LOW HIGH
Differential to Differential Non Inverting
0
1
0
X HIGH LOW
Differential to Differential Non Inverting
0
0
Biased; NOTE 1 X LOW HIGH Single Ended to Differential Non Inverting
0
1
Biased; NOTE 1 X HIGH LOW Single Ended to Differential Non Inverting
0
Biased; NOTE 1
0
X HIGH LOW Single Ended to Differential Inverting
0
Biased; NOTE 1
1
X LOW HIGH Single Ended to Differential Inverting
1
X
X
0 LOW HIGH Single Ended to Differential Non Inverting
1
X
X
1 HIGH LOW Single Ended to Differential Non Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
85214AGI
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 1, 2005