ICS85214I Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1, 2
Q0, nQ0 Output
Differential output pair. HSTL interface levels.
3, 4
Q1, nQ1 Output
Differential output pair. HSTL interface levels.
5, 6
Q2, nQ2 Output
Differential output pair. HSTL interface levels.
7, 8
Q3, nQ3 Output
Differential output pair. HSTL interface levels.
9, 10
Q4, nQ4 Output
Differential output pair. HSTL interface levels.
11
GND
Power
Power supply ground.
12
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0, nCLK0 input. LVTTL / LVCMOS interface levels.
13, 17
nc
Unused
No connect.
14
nCLK0
Input Pullup Inverting differential clock input.
15
CLK0
Input Pulldown Non-inverting differential clock input.
16
CLK1
Input Pulldown Clock input. LVTTL / LVCMOS interface levels.
18
V_DD
Power
Core supply pin.
Synchronizing clock enable. When LOW, clock outputs follow clock input.
19
nCLK_EN Input Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
20
V_DDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
85214AGI
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 1, 2005