ICS8432-111 Datasheet, PDF (3/17 Pages) Integrated Circuit Systems – 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
7
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
Input
Input
Pullup
M counter/divider inputs. Data latched on LOW-to-HIGH transistion
Pulldown ^{of nP_LOAD input. LVCMOS/LVTTL interface levels.}
Input
Pulldown
Determines output divider value as defined in Table 3C
Function Table. LVCMOS/LVTTL interface levels.
Unused
No connect.
8, 16
9
10
11,
12
13
14, 15
17
18
19
20
21
22
23
V_EE
TEST
V
CC
FOUT/2,
nFOUT/2
V_CCO
FOUT, nFOUT
MR
S_CLOCK
S_DATA
S_LOAD
V_CCA
CLK_SEL
TEST_CLK
Power
Output
Power
Output
Power
Output
Input
Input
Input
Input
Power
Input
Input
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
Half frequency differential output for the synthesizer.
3.3V LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Pulldown
Pulldown
Pulldown
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
outputs nFOUTx to go high. When logic LOW, the internal dividers
are the outputs are enabled. Assertion of MR does not effect loaded
M, N, and T values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pullup
Selects between differential clock input or test input as the PLL
reference source. LVCMOS/LVTTL interface levels. Selects CLK,
nCLK inputs when HIGH. Selects TEST_CLK when LOW.
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
24
CLK
Input Pulldown Non-inverting differential clock input.
25
nCLK
Input Pullup Inverting differential clock input.
Parallel load input. Determines when data present at M8:M0 is loaded
26
nP_LOAD
Input Pulldown into M divider, and when data present at N1:N0 sets the N output
divider value. LVCMOS/LVTTL interface levels.
27
VCO_SEL
Input
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
8432CY-111
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
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3
REV. B MARCH 3, 2004