ICS8432-111 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz clock input. Valid PLL loop divider
values for different input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-111 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A differential clock input is used as the input to the
ICS8432-111. This input is fed into the phase detector. A
25MHz clock input provides a 25MHz phase detector refer-
ence frequency. The VCO of the PLL operates over a range
of 250MHz to 700MHz. The output of the M divider is also
applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjust-
ing the VCO control voltage. Note, that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8432-111 support two
input modes to program the PLL M divider and N output divider.
The two input operational modes are parallel and serial. Figure1
shows the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a se-
rial event occurs. As a result, the M and N bits can be hardwired
to set the M divider and N output divider to a specific default
state that will automatically occur during power-up. The TEST
output is LOW when operating in the parallel input mode. The
relationship between the VCO frequency, the input frequency
and the M divider is defined as follows: fVCO = f_IN x M
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. When
the input clock is at 25MHz, the valid M values for which the
PLL will achieve lock are defined as 10 ≤ M ≤ 28. The frequency
out
is
defined
as
follows:
fOUT
=
fVCO
N
=
f_IN
x
M
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N out-
put divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each rising
edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T1 and T0.The internal reg-
isters T0 and T1 determine the state of the TEST output as follows:
T1 T0
TEST Output
00
LOW
01
S_Data, Shift Register Input
10
Output of M divider
11
CMOS Fout/2
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
SERIAL LOADING
T1 T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
M, N
PARALLEL LOADING
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8432CY-111
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2
REV. B MARCH 3, 2004