ICS8432-111 Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
ICS
HiPerClockS™
The ICS8432-111 is a general purpose, dual out-
put Differential-to-3.3V LVPECL High Frequency
Synthesizer and a member of the HiPerClockS™
• Dual differential 3.3V LVPECL outputs
• Selectable differential CLK, nCLK pair or LVCMOS TEST_CLK
family of High Performance Clocks Solutions • CLK, nCLK pair can accept the following differential input
from ICS. The ICS8432-111 has a selectable levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
differential CLK, nCLK pair or LVCMOS/LVTTL TEST_CLK. The
TEST_CLK input accepts LVCMOS or LVTTL input levels
and translates them to 3.3V LVPECL levels. The CLK, nCLK
• TEST_CLK can accept the following input types:
LVCMOS or LVTTL
pair can accept most standard differential input levels.The • Maximum FOUT frequency: 700MHz
VCO operates at a frequency range of 200MHz to 700MHz. Maximum FOUT/2 frequency: 350MHz
The VCO frequency is programmed in steps equal to the value
of the input differential or single ended reference frequency. ^{• CLK, nCLK or TEST_CLK input frequency: 40MHz}
Output frequencies up to 700MHz for FOUT and 350MHz for
FOUT/2 can be programmed using the serial or parallel
interfaces to the configuration logic. The low phase noise
characteristics and the multiple frequency outputs of the
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter
and VCO frequency multiplier and dividers
ICS8432-111 makes it an ideal clock source for Fibre Channel _{• RMS period jitter: 5ps (maximum)}
1 and 2, and Infiniband applications.
• Cycle-to-cycle jitter: 40ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
VCO_SEL
CLK_SEL
TEST_CLK
0
CLK
1
nCLK
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
PLL
PHASE DETECTOR
VCO
÷M
÷1
0 ^÷2
÷4
÷8
1
÷2
CONFIGURATION
INTERFACE
LOGIC
PIN ASSIGNMENT
FOUT
nFOUT
FOUT/2
nFOUT/2
32 31 30 29 28 27 26 25
M5 1
M6 2
M7 3
M8 4
N0 5
N1 6
nc 7
VEE 8
ICS8432-111
24 CLK
23 TEST_CLK
22 CLK_SEL
2 1 VCCA
20 S_LOAD
19 S_DATA
18 S_CLOCK
17 MR
9 10 11 12 13 14 15 16
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8432CY-111
www.icst.com/products/hiperclocks.html
1
REV. B MARCH 3, 2004