ICS671-03 Datasheet, PDF (3/4 Pages) Integrated Circuit Systems – 3.3 Volt Zero Delay, Low Skew Buffer

PRELIMINARY INFORMATION
ICS671-03
3.3 Volt Zero Delay, Low Skew Buffer
Electrical Specifications
Parameter
Conditions
Minimum Typical Maximum
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
-0.5
7
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
CLKIN and FBIN Inputs
-0.5
5.5
Electrostatic Discharge
MIL-STD-883
2000
Ambient Operating Temperature
-40
85
Soldering Temperature
Max of 10 seconds
260
Junction temperature
150
Storage temperature
-65
150
DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Operating Voltage, VDD
3.00
3.60
Input High Voltage, VIH
2
Input Low Voltage, VIL
0.8
Output High Voltage, VOH
IOH=-12 mA
2.4
Output Low Voltage, VOL
IOL=12 mA
0.4
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
Operating Supply Current, IDD (Note 2)
No Load, S2=1, S1=1
70
Power Down Supply Current, IDD
CLKIN=0, S2=0, S1=1
1.3
CLKIN=0 (Note 3)
1.3
Short Circuit Current
Each output
±50
Input Capacitance
S2, S1, FBIN
5
AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Input Clock Frequency
See table on page 2
10
133
Output Clock Frequency
See table on page 2
10
133
Output Clock Rise Time, CL=30pF
0.8 to 2.0V
1.5
Output Clock Fall Time, CL=30pF
2.0 to 0.8V
1.25
Output Clock Duty Cycle, VDD=3.3V
At VDD/2
45
50
55
Device to Device Skew, equally loaded
rising edges at VDD/2
700
Output to Output Skew, equally loaded
rising edges at VDD/2
200
Input to Output Skew, FBIN to CLKA4, S1=1, S0 =1
(Note 2)
rising edges at VDD/2
±250
Maximum Absolute Jitter
130
Cycle to Cycle Jitter, 30pF loads
300
PLL Lock Time (Note 4)
1.0
Units
V
V
V
°C
°C
°C
°C
V
V
V
V
V
V
mA
mA
mA
mA
pF
MHz
MHz
ns
ns
%
ps
ps
ps
ps
ps
ms
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the
device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may
affect device reliability.
2. With CLKIN = 100 MHz, FBIN to CLKA4, all outputs at 100 MHz.
3. When there is no clock signal present at CLKIN, the ICS671-03 will enter a power down mode. The PLL is
stopped and the outputs are tri-state.
4. With VDD at a steady state, and valid clocks at CLKIN and FBIN.
MDS 671-03 A
3
Revision 072501
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