ICS671-03 Datasheet, PDF (2/4 Pages) Integrated Circuit Systems – 3.3 Volt Zero Delay, Low Skew Buffer

Pin Assignment
PRELIMINARY INFORMATION
ICS671-03
3.3 Volt Zero Delay, Low Skew Buffer
CLKIN 1
CLKA1 2
CLKA2 3
VDD 4
GND 5
CLKB1 6
CLKB2 7
S2 8
16 FBIN
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
16 pin narrow (150 mil) SOIC
Output Clock Mode Select Table
S2 S1
CLKA1:A4
CLKB1:B4
0
0
Tri-state (Note 1)
Tri-state (Note 1)
0
1
Stopped Low
Stopped Low
1
0
Running
Running
1
1
Running
Running
Notes: 1. Outputs are in high impedance state with weak pulldowns.
2. Buffer mode only; not zero delay between input and output.
Pin Descriptions
A & B Source
PLL
none
CLKIN (Note 2)
PLL
PLL Status
ON
OFF
OFF
ON
Number
1
2, 3, 14, 15
4, 13
5, 12
6, 7, 10, 11
8
9
16
Name
CLKIN
CLKA1:A4
VDD
GND
CLKB1:B4
S2
S1
FBIN
Type
I
O
P
P
O
I
I
I
Description
Clock Input. (5 V tolerant)
Clock Outputs A1:A4. See above table. Outputs have weak pulldown resistors.
Power supply. Connect both pins to 3.3 V.
Connect to ground.
Clock Outputs B1:B4. See above table. Outputs have weak pulldown resistors.
Select input 2. See table above. Internal pull-up.
Select input 1. See table above. Internal pull-up.
Feedback Input. Connect to any output under normal operation. (5 V tolerant)
Key: I = Input; O = output; P = power supply connection. Outputs have a weak internal pull-down when in tri-state
mode.
External Components
The ICS671-03 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND on pins 13 and 12, as
close to the device as possible. A series termination resistor of 33 Ω may be used close to each clock output pin to
reduce reflections.
MDS 671-03 A
2
Revision 072501
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