ICS650-14B Datasheet, PDF (3/4 Pages) Integrated Circuit Systems – Networking System Clock

PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Referenced to GND
Ambient Operating Temperature
Ambient Operating Temperature
Industrial "I" version
Soldering Temperature
Max of 20 seconds
Storage temperature
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Clock Input
Input Low Voltage, VIL, X1 pin only
Clock Input
Input High Voltage, VIH, SEL pins only
Input Low Voltage, VIL, SEL pins only
Input High Voltage, VIH, OE pin only
Input Low Voltage, VIL, OE pin only
Output High Voltage, VOH
IOH=-12mA
Output Low Voltage, VOL
IOL=12mA
Output High Voltage, VOH, CMOS level
IOH=-8mA
Operating Supply Current, IDD
No Load
Short Circuit Current
Each output
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Frequency
Output Clock Rise Time
0.8 to 2.0V
Output Clock Fall Time
2.0 to 0.8V
Output Clock Duty Cycle
At VDD/2
Frequency error
All clocks
Absolute Jitter, short term
Variation from mean
Minimum Typical Maximum Units
7
V
-0.5
VDD+0.5 V
0
70
°C
-40
85
°C
260
°C
-65
150
°C
3
VDD/2 + 1
VDD - 0.5
2.0
2.4
VDD-0.4
TBD
±50
5.5
V
V
VDD/2 - 1 V
V
0.5
V
V
0.8
V
V
0.4
V
V
mA
mA
25.000
MHz
1.5
ns
1.5
ns
45
50
55
%
0
ppm
TBD
ps
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. CMOS level input, nominal trip point is VDD/2 for 3.3 V or 5 V operation.
External Components
The ICS650R-14B requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between each VDD and GND on Pins 4 and 6, and Pins 16 and
14, as close to the ICS650R-14B as possible. A series termination resistor of 33 Ω may be used for each
clock output. The 25.00 MHz crystal must be connected as close to the chip as possible. The crystal should
be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these
capacitors is given by the following equation, where C_L is the crystal load capacitance: Crystal caps (pF) =
(C_L-6) x 2. So for a crystal with 16 pF load capacitance, two 20 pF caps should be used.
MDS 650-14B A
3
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•[phone]tel• www.icst.com