ICS650-14B Datasheet, PDF (2/4 Pages) Integrated Circuit Systems – Networking System Clock

PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Pin Assignment
SELB0 1
X2 2
X1/ICLK ³
VDD 4
SELB1 5
GND ₆
CLKB 7
CLKC 8
CLKA5 9
25M 10
20 SELC
19 SELA0
18 CLKA2
17 CLKA3
16 VDD
15 _SELA1
14 GND
13 CLKA4
12 CLKA1
11 _OE
20 pin (150 mil) SSOP
Pin Descriptions
Table 1
SELA1
0
0
0
M
M
M
1
1
1
SELA0
0
M
1
0
M
1
0
M
1
CLKA1:4
33.33
50
66.67
100
33.33
50
33.33
25
66.67
CLKA5
66.66
75
133.33
33.33
83.33
125
100
75
100
Table 2
SELB1
0
0
0
1
1
1
SELB0
0
M
1
0
M
1
CLKB
30
27
48
83.33
19.44
80
Table 3
SELC
0
M
1
CLKC
CLKB/4
62.5
125
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
SELB0
X2
X1/ICLK
VDD
SELB1
GND
CLKB
CLKC
CLKA5
25M
OE
CLKA1
CLKA4
GND
SELA1
VDD
CLKA3
CLKA2
SELA0
SELC
Type
TI
XO
XI
P
I(Pu)
P
O
O
O
O
I(Pu)
O
O
P
TI
P
O
O
TI
TI
Description
Select pin for CLKB. See Table 2.
Crystal connection. Connect to 25 MHz crystal or leave unconnected for a clock input.
Crystal connection. Connect to 25 MHz fundamental crystal or clock input.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
Select pin for CLK B. See table 2.
Connect to ground.
Selectable clock output. See Table 2.
Selectable clock output. See Table 3.
Selectable clock output. See Table 1.
25.0 MHz clock output.
Output Enable. Tri-states all output clocks when low. Internal pull-up.
Selectable clock output. See Table 1.
Selectable clock output. See Table 1.
Connect to ground.
Select pin for CLKA1:4 and CLKA5 outputs. See Table 1.
Connect to +3.3V or +5.0V. Must be same as other VDDs.
Selectable clock output. See Table 1.
Selectable clock output. See Table 1.
Select pin for CLKA1:4 and CLKA5 outputs. See Table 1.
Select pin for CLKC output. See Table 3.
Key: XI, XO = crystal connections; I = Input; I(Pu) = Input with pull up O = Output; P = power supply connection; TI = tri level input
MDS 650-14B A
2
Revision 082800
Printed 11/15/00
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