ICS650-14B Datasheet, PDF (1/4 Pages) Integrated Circuit Systems – Networking System Clock

PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Description
The ICS650-14B is a low cost, low jitter, high
performance clock synthesizer customized for
networking systems applications. Using analog
Phase-Locked Loop (PLL) techniques, the device
accepts a 25.0 MHz clock or fundamental mode
crystal input to produce multiple output clocks of
one fixed 25.0 MHz, a four (plus one) frequency
selectable bank, and two frequency selectable
clocks. All output clocks are frequency locked
together. The ICS650R-14B outputs
all have 0 ppm synthesis error.
Block Diagram
Features
• Packaged in 20 pin (150 mil) SSOP (QSOP)
• 25.00 MHz fundamental crystal or clock input
• One fixed output clock of one 25.0 MHz
• One bank of four frequency selectable
output clocks
• Three frequency selectable clock outputs
• Zero ppm synthesis error in all clocks
• Ideal for networking systems
• Full CMOS output swing
• Advanced, low power, sub-micron CMOS process
• 3.0V to 5.5V operating voltage
• Industrial temperature range available
2
SELA 0:1
SELB 0:1 ²
SELC
VDD GND
22
Clock Synthesis
and Control
Circuitry
25.00 MHz
crystal or clock
X1/ICLK
X2
Clock
Buffer/
Crystal
Oscillator
Output ⁴
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
CLKA 1:4
CLKA5
CLKB
CLKC
Output
Buffer
25.00 MHz
OE (All outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
MDS 650-14B A
1
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•[phone]tel• www.icst.com