PSICS9169-01 Datasheet, PDF (2/10 Pages) Integrated Circuit Systems – Frequency Generator and Integrated Buffers for Intel Pentium and Pentium ProTM mPs

ICS9169-01
Pin Configuration
28 Pin SOIC
28 Pin SSOP
Functionality
FS1 FS0
*VCO
0
0 230/33x X1
0
1 212/23x X1
1
0 176/21x X1
1
1
Test mode
X1, REF
(MHz)
14.31818
14.31818
14.31818
TCLK
PCLK(0:3)
(MHz)
50 (49.7)
66 (66.5)
60 (59.9)
TCLK/2
*VCO range is limited from 60 - 200 MHz
PCLK(0:3)
VCO/2
TCLK/2
BCLK(0:5)
PCLK/2
TCLK/4
48 MHz
48 MHz
TCLK/2
Pin Descriptions
PIN NUMBER
2
3
4, 11, 23
17
1, 8, 26
PIN NAME
X1
X2
GND
GND
VDD
14, 20
VDD
6, 7, 9, 10
13, 12
15, 16, 18
19, 21, 22
5
24
PCLK(0:3)
FS(0:1)
BCLK(0:5)
OEN
48MHz
28, 27, 25
REF(0:2)
TYPE
IN
OUT
PWR
PWR
DESCRIPTION
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 12.16 MHz crystal, nominally 14.31818
XTAL output which includes XTAL load capacitance.
Ground for logic, PCLK and fixed frequency output buffers.
Ground for BCLK output buffers.
PWR Power for logic, PCLK and fixed frequency output buffers.
PWR
OUT
IN
OUT
IN
OUT
OUT
Power for BCLK output buffers.
Processor clock outputs which are a multiple of the input reference frequency
as shown in the table above.
Frequency multiplier select pins. See table above. These inputs have internal
pull-up devices.
Bus clock outputs are fixed at 1/2 the PCLK frequency.
OEN tristates all outputs when low. This input has an internal pull-up device.
Fixed 48 MHz clock (with 14.318 MHz input).
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
Note 1: BCLK buffers cannot be supplied with 5 volts (pins 14 and 20) if CPU and fixed frequencies (pins 1, 8, and 26) are being
supplied with 3.3 volts
2