ICS950703 Datasheet, PDF (2/24 Pages) Integrated Circuit Systems – PROGRAMMABLE TIMING CONTROL HUB FOR P4

Integrated
Circuit
Systems, Inc.
ICS950703
General Description
The ICS950703 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with Rambus RDRAM
memory. It provides all necessary clock signals for such a system.
The ICS950703 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially
programmable I²C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios,
selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/
N control can configure output frequency with resolution up to 0.1MHz increment.This part also provides 128 frequency selections
via ICS QuadROM^TM technology as an alternate to M/N programming.
Block Diagram
PLL2
Frequency
Dividers
48MHZ (1:0)
X1
XTAL
X2
MULTSEL (1:0)
FS (3:0)
SEL100_133#
SDATA
SCLK
PD#
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
REF (1:0)
4 ^{CPUCLKT (3:0)}
4 ^{CPUCLKC (3:0)}
PCICLK (9 :0)
MREF
MREF_B
3V66 (3:0)
I REF
Power Groups
Pin Number
AVDD
GND
4
7
27
24
38
37
VDD
GND
10, 16, 22
13, 19
29, 36
32, 33
43, 49
40, 46
56
53
0690D—05/14/04
Description
REF output, Crystal
48MHz fixed, Fixed PLL
CPU PLL, CPU Master Clock,
--
PCI outputs
3V66 outputs
CPU Outputs, IREF, MULTSEL
MREF outputs
2