ICS950703 Datasheet, PDF (15/24 Pages) Integrated Circuit Systems – PROGRAMMABLE TIMING CONTROL HUB FOR P4

Integrated
Circuit
Systems, Inc.
ICS950703
I²C Table: VCO Frequency Control Register
Byte 12
Pin #
Name
Control Function
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
NDiv7
NDiv6
NDiv5
NDiv4
NDiv3
NDiv2
NDiv1
NDiv0
The decimal
representation of N
Div (8:0) +8 is equal
to VCO divider
value. Default at
power up = latch-in
or Byte 0 Rom table.
Type
RW
RW
RW
RW
RW
RW
RW
RW
I²C Table: Spread Spectrum Control Register
Byte 13
Bit 7
Bit 6
Pin #
-
-
Name
SSP7
SSP6
Control Function
These Spread
Spectrum bits will
Bit 5
-
SSP5
program the spread
Bit 4
-
SSP4
pecentage. It is
Bit 3
-
SSP3
recommended to
Bit 2
-
SSP2
use ICS Spread %
Bit 1
-
SSP1
table for spread
Bit 0
-
SSP0
programming.
Type
RW
RW
RW
RW
RW
RW
RW
RW
I²C Table: Spread Spectrum Control Register
Byte 14
Pin #
Name
Control Function
Bit 7
-
Reserved
Reserved
Bit 6
-
Reserved
Reserved
Bit 5
-
SSP13
Bit 4
-
SSP12 ^{It is recommended to}
Bit 3
-
SSP11
use ICS Spread %
Bit 2
-
SSP10
table for spread
Bit 1
-
SSP9
programming.
Bit 0
-
SSP8
Type
R
R
R
RW
RW
RW
RW
RW
I²C Table: Output Divider Control Register
Byte 15
Pin #
Name
Bit 7
-
Reserved
Bit 6
-
Reserved
Bit 5
-
Reserved
Bit 4
-
Reserved
Bit 3
-
CPUDiv3
Bit 2
-
CPUDiv2
Bit 1
-
CPUDiv1
Bit 0
-
CPUDiv0
Control Function
Reserved
Reserved
Reserved
Reserved
CPU divider ratio
can be configured
via these 4 bits
individually.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
0
1
PWD
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
0
1
PWD
-
-
0
-
-
0
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
0
1
-
-
-
-
-
-
-
-
See Table 4: Divider
Ratio Combination
Table
PWD
X
X
X
X
X
X
X
X
0690D—05/14/04
15