ICS950227 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950227
Pin Description
PIN NUMBER
1, 8, 14, 19, 26,
32, 37, 46, 50
2
3
7, 6, 5
4, 9, 15, 20, 27,
31, 36, 41, 47
18, 17, 16, 13,
12,11, 10
24, 23, 22, 21
25
28
29
30
33
34
35
38
39
40
42
43
44, 48, 51
45, 49, 52
53
55, 54
56
PIN NAME
VDD
X1
X2
PCICLK_F (2:0)
GND
PCICLK (6:0)
3V66 (5:2)
PD#
Vtt_PWRGD#
SDATA
SCLK
3V66_0
PCI_STOP#
3V66_1/VCH_CLK
48MHz_DOT
48MHz_USB
FS2
I REF
MULTSEL0
CPUCLKC (2:0)
CPUCLKT (2:0)
CPU_STOP#
FS (1:0)
REF
TYPE
DESCRIPTION
PWR 3.3V power supply
X2 Crystal
Input
14.318MHz Crystal input
X1 Crystal
Output
14.318MHz Crystal output
OUT
Free running PCI clock not affected by PCI_STOP#
for power management.
PWR Ground pins for 3.3V supply
OUT
OUT
IN
IN
I/O
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
OUT
PCI clock outputs
66MHz reference clocks, from internal VCO
Invokes power-down mode. Active Low.
This 3.3V LVTTL input is a level sensitive strobe used to
determine when FS(2:0) and MULTISEL0 inputs are valid
and are ready to be sampled
(active low)
Data pin for I²C circuitry 5V tolerant
Clock pin of I²C circuitry 5V tolerant
66MHz reference clocks, from internal VCO
Halts PCICLK clocks at logic 0 level, when input low except
PCICLK_F which are free running
3.3V output selectable through I²C to be 66MHz from internal VCO
or
48MHz (non-SSC)
48MHz output clock for DOT
48MHz output clock for USB
Special 3.3V input for Mode selection, cannot be logic 1
This pin establishes the reference current for the CPUCLK pairs.
This pin requires a fixed precision resistor tied to ground in order to
establish the appropriate current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementory" clocks of differential pair CPU outputs. These are
current outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
Halts CPUCLK clocks at logic 0 level, when input low
Frequency select pins
14.318MHz reference clock.
Power Groups
(Analog)
VDDA = Analog Core PLL1
VDDREF = REF, Xtal
VDD48 = 48MHz, PLL
0641D—07/03/03
(Digital)
VDDPCI
VDD3V66
VDDCPU
2