ICS93722 Datasheet, PDF (2/6 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Zero Delay Buffer

ICS9372 2
Pin Descriptions
PIN NUMBER
PIN NAME
6, 11, 15, 28 GND
27, 25, 16, 14, 5, 1 CLKC(5:0)
26, 24, 17, 13, 4, 2 CLKT(5:0)
3, 12, 23
VDD
7
SCLK
8
CLK_INT
9, 18, 21
N/C
10
VDDA
19
FB_OUTT
20
FB_INT
22
SDATA
TYPE
DESCRIPTION
PWR Ground
OUT "Complementary" clocks of differential pair outputs.
OUT "True" Clock of differential pair outputs.
PWR Power supply 2.5V
IN Clock input of I²C input, 5V tolerant input
IN "True" reference clock input
- Not connected
PWR
OUT
IN
IN
Analog power supply, 2.5V
"True" Feedback output, dedicated for external feedback. It switches at
the same frequency as the CLK. This output must be wired to FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
Data input for I²C serial input, 5V tolerant input
Bytes 0 to 4 are reserved power up default = 1.
Byte 5: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
2, 1
4, 5
-
-
13, 14
17, 16
-
-
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
CLK0 (T&C)
Reserved
Reserved
Reserved
CLK2 (T&C)
CLK3 (T&C)
Reserved
Reserved
Note: PWD = Power Up Default
Byte 6: Output Control
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
1 Reserved
Bit6 -
1 Reserved
Bit5 -
1 Reserved
Bit4 -
1 Reserved
Bit3
24,
25
1 CLK4 (T&C)
Bit2 -
1 Reserved
Bit1
26,
27
1 CLK5 (T&C)
Bit0 -
1 Reserved
0539E—07/18/03
2