ICS93722 Datasheet, PDF (1/6 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Zero Delay Buffer

Integrated
Circuit
Systems, Inc.
ICS9372 2
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Recommended Application:
DDR Zero Delay Clock Buffer
Product Description/Features:
• Low skew, low jitter PLL clock driver
• I²C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• 3.3V tolerant CLK_INT input
Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (66MHz):<110ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 650ps - 950ps
• DUTY CYCLE: 49.5% - 50.5%
Pin Configuration
CLKC0
1
CLKT0
2
VDD
3
CLKT1
4
CLKC1
5
GND
6
SCLK
7
CLK_INT
8
N/C
9
VDDA 10
GND 11
VDD 12
CLKT2 13
CLKC2 14
28 GND
27 CLKC5
26 CLKT5
25 CLKC4
24 CLKT4
23 VDD
22 SDATA
21 N/C
20 FB_INT
19 FB_OUTT
18 N/C
17 CLKT3
16 CLKC3
15 GND
28-Pin SSOP
Block Diagram
SCLK
SDATA
Control
Logic
FB_INT
PLL
CLK_INT
0539E—07/18/03
FB_OUTT
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
Functionality
INPUTS
AVDD CLK_INT
2.5V
(nom)
L
2.5V
(nom)
H
2.5V
(nom)
<20MHz
OUTPUTS
PLL State
CLKT CLKC FB_OUTT
L
H
L
on
H
L
H
on
Z
Z
Z
off