ICS9248-134 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – Frequency Timing Generator for PENTIUM II/III Systems

ICS9248-134
General Description
The ICS9248-134 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the
ICS9212-01.
Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-134
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
The CPU/2 clocks are inputs to the DRCG.
Pin Descriptions
Pin number
Pin name
1, 7, 13, 19, 25, 31,
36, 41, 45
GND
2
REF0
REF1
3
SEL24_48
4, 10, 16, 23, _VDD
28, 35
5
X1
6
X2
PCICLK_F
8
FS0
PCICLK0
9
FS1
PCICLK1
11
FS2
12
PCICLK2
FS3
14, 15, 17, 18, 20,
21, 22
PCICLK (9:3)
24
PD#
26
27
29
30
32, 33, 34
37, 38, 40
42
39, 43, 48
44, 46, 47
24_48MHz
48M H z
FS4
SCLK
S D A TA
3V66 (2:0)
CPUCLK (2:0)
C P U /2
VDDL
IOAPIC (2:0)
Type
PWR
OUT
OUT
IN
PWR
IN
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
IN
IN
I/O
OUT
OUT
OUT
PWR
OUT
D es crip tion
G round pins
14.318M Hz reference clock outputs at 3.3V
14.318M Hz reference clock outputs at 3.3V
Logic input to select 24 or 48M Hz for pin 26 output
Power pins 3.3V
X TAL_IN 14.318M Hz crystal input
X TAL_O UT Crystal output
Free running PCI clock at 3.3V . Synchronous to CPU clocks. Not
affected by the PCI_STOP# input.
Logic - input for frequency selection
PCI clock output at 3.3V . Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V . Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V . Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the output clocks
are held at a Low state.
24 or 48M Hz output selectable by
SEL24_48# (0=48MHz 1=24M Hz)
Fixed 48M Hz clock output. 3.3V
Logic - input for frequency selection
Clock input of I²C input
D ata pin for I²C circuitry 5V tolerant
3.3V clock outputs. These outputs are stopped when CPU_STOP#
is driven active..
H ost bus clock output at 2.5V.
2.5V clock outputs at 1/2 CPU frequency.
Power pins for the CPU, CPU/2 & IO APIC clocks. 2.5V
IOAPIC clocks at 2.5V. Synchronous with CPU CLKs.
2