ICS9173-01 Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – Video Genlock PLL

AV9173- 01
Pin Configuration
8-Pin DIP or SOIC
Pin Descriptions
PIN
NUMBE-
R
1
2
3
4
5
6
7
8
PIN NAME
FBIN
IN
GND
FS0
OE
CLK1
VDD
CLK2
TYPE
Input
Input
—
Input
Input
Output
—
Output
DESCRIPTION
Feedback Input
Input for reference sync pulse
Ground
Frequency Select 0 input
Output Enable
Clock Output 1
Power Supply (+5V)
Clock Output 2 (Divided-by-2 from Clock 1)
Table 1: Allowable Input Frequency to Output Frequency (Outputs in MHz)
fIN (kHz)
12 ≤ fIN ≤ 14 kHz
14 < fIN ≤ 17 kHz
17 < fIN ≤ 30 kHz
30 < fIN ≤ 35 kHz
35 < fIN ≤ 1000 kHz
fOUT for FS = 0 (MHz)
CLK1 Output
CLK2 Output
44.0 to 75
22.0 to 37.5
30.0 to 75
15.0 to 37.5
25.0 to 75
12.5 to 37.5
15.0 to 75
7.5 to 37.5
10.0 to 75
5.0 to 37.5
fOUT for FS = 1 (MHz)
CLK1 Output
CLK2 Output
11.0 to 18.75
5.5 to 9.375
7.5 to 18.75
3.75 to 9.375
6.25 to 18.75
3.125 to 9.375
3.75 to 18.75
1.875 to 9.375
2.5 to 18.75
1.25 to 9.375
2