ICS9148-32 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – Pentium/ProTM System Clock Chip

ICS9148-32
Pin Descriptions
PIN NUMBER
1
2, 47
3
4
5
6, 12, 18
7
8, 10, 11, 13, 14, 16, 17
9, 15
19, 33
20, 32
21
22
23
24
25
26
27
28¹
29¹
30¹
31¹
37, 41
34, 38
35, 36, 39, 40
42
43
44, 45
46
PIN NAME
REF0/SEL48#
REF (1:2)
GND1
X1
X2
GND2
PCICLK_F
PCICLK (0:6)
VDD2
VDD
GND
VDD3
48MHz
24/48MHz#
GND3
SEL100/66.6#
SCLK
SDATA
SPREAD#
PD#
CPU_STOP#
PCI_STOP#
VDDL2
GNDL2
CPUCLK (3:0)
N/C
GNDL1
IOAPIC (0:1)
VDDL1
TYPE
OUT/IN
OUT
PWR
IN
OUT
PWR
OUT
OUT
PWR
PWR
PWR
PWR
OUT
OUT
PWR
IN
IN
IN
IN
IN
IN
IN
PWR
PWR
OUT
-
PWR
OUT
PWR
DESCRIPTION
14.318MHz clock output / Latched input at power up. When
low, pin 23 is 48MHz.
14.318MHz clock output
Ground for REF outputs
XTAL_IN 14.318MHz Crystal input, has internal 33pF load
cap and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Isolated power for core, nominally 3.3V
Isolated ground for core
Power for 48MHz outputs, nominally 3.3V
48MHz output
Fixed clock output. 24MHz if pin1=1 at power up
48MHz if pin 1=0 at power up
Ground for 48MHz outputs
Select pin for enabling 100MHz or 66.6MHz
H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz)
Clock input for I²C input
Data input for I²C input
Enables Spread Spectrum feature when LOW
Powers down chip, active low
Halts CPU clocks at logic "0" level when low
Halts PCI Bus at logic "0" level when low
Power for CPU outputs, nominally 2.5V
Ground for CPU outputs.
CPU and Host clock outputs, nominally 2.5V
Not internally connected
Ground for IOAPIC outputs
IOAPIC outputs (14.318MHz) nominally 2.5V
Power for IOAPIC outputs, nominally 2.5V
Select Functions
Functionality
Tristate
Testmode
Spread Spectrum
CPU
HI - Z
TCLK/2¹
Modulated²
PCI,
PCI_F
HI - Z
TCLK/6¹
Modulated²
REF
HI - Z
TCLK¹
14.318MHz
IOAPIC
HI - Z
TCLK¹
14.318MHz
48 MHz
Selection
HI - Z
TCLK/2¹
48.0MHz
2