ICS8534-01 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8534-01
LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 16, 17, 32,
33, 48, 49, 64
V_CCO
Power
Output supply pins.
2, 3, 12, 13
nc
Unused
No connect.
4
V_CC
Power
Core supply pin.
5
CLK
Input Pulldown Non-inverting differential clock input pair.
6
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input pair. Pulled to ²/₃ V_CC.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
7
CLK_SEL
Input Pullup When LOW, selects CLK, nCLK inputs.
LVCMOS / LVTTL interface levels.
8
PCLK
Input Pulldown Non-inverting differential LVPECL clock input pair.
9
nPCLK
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input pair. Pulled to ²/₃ V_CC.
10
V
Power
EE
Power supply ground.
Output enable. When logic HIGH, the outputs are enabled (default).
11
OE
Input Pullup When logic LOW, the outputs are disabled and drive differential low:
Qx = LOW, nQx = HIGH. LVCMOS / LVTTL interface levels.
14, 15
nQ21, Q21 Output
Differential clock outputs. LVPECL interface levels.
18, 19
nQ20, Q20 Output
Differential clock outputs. LVPECL interface levels.
20, 21
nQ19, Q19 Output
Differential clock outputs. LVPECL interface levels.
22, 23
nQ18, Q18 Output
Differential clock outputs. LVPECL interface levels.
24, 25
nQ17, Q17 Output
Differential clock outputs. LVPECL interface levels.
26, 27
nQ16, Q16 Output
Differential clock outputs. LVPECL interface levels.
28, 29
nQ15, Q15 Output
Differential clock outputs. LVPECL interface levels.
30, 31
nQ14, Q14 Output
Differential clock outputs. LVPECL interface levels.
34, 35
nQ13, Q13 Output
Differential clock outputs. LVPECL interface levels.
36, 37
nQ12, Q12 Output
Differential clock outputs. LVPECL interface levels.
38, 39
nQ11, Q11 Output
Differential clock outputs. LVPECL interface levels.
40, 41
nQ10, Q10 Output
Differential clock outputs. LVPECL interface levels.
42, 43
nQ9, Q9 Output
Differential clock outputs. LVPECL interface levels.
44, 45
nQ8, Q8 Output
Differential clock outputs. LVPECL interface levels.
46, 47
nQ7, Q7 Output
Differential clock outputs. LVPECL interface levels.
50, 51
nQ6, Q6 Output
Differential clock outputs. LVPECL interface levels.
52, 53
nQ5, Q5 Output
Differential clock outputs. LVPECL interface levels.
54, 55
nQ4, Q4 Output
Differential clock outputs. LVPECL interface levels.
56, 57
nQ3, Q3 Output
Differential clock outputs. LVPECL interface levels.
58, 59
nQ2, Q2 Output
Differential clock outputs. LVPECL interface levels.
60, 61
nQ1, Q1 Output
Differential clock outputs. LVPECL interface levels.
62, 63
nQ0, Q0 Output
Differential clock outputs. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8534AY-01
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 19, 2004