ICS848004I Datasheet, PDF (2/11 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS848004I
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1, 2
nQ1, Q1 Output
Differential output pair. SSTL_2 interface levels.
3, 22
4, 5
V_DDO
Q0, nQ0
Power
Ouput
Output supply pins.
Differential output pair. SSTL_2 interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
6
MR
Input
Pulldown
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
7
nPLL_SEL Input Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
8, 18
nc
Unused
No connect.
9
10, 12
V_DDA
F_SEL0,
F_SEL1
Power
Analog supply pin.
Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
11
13, 14
V_DD
XTAL_OUT,
XTAL_IN
Power
Input
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
15, 19
GND
Power
Power supply ground.
16
TEST_CLK Input Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
17 nXTAL_SEL Input Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
20, 21 nQ3, Q3 Output
Differential output pair. SSTL_2 interface levels.
23, 24 Q2, nQ2 Output
Differential output pair. SSTL_2 interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
848004AGI
www.icst.com/products/hiperclocks.html
2
REV. A AUGUST 18, 2005