ICS848004I Datasheet, PDF (1/11 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS848004I
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS848004I is a 4 output SSTL_2
ICS
Synthesizer optimized to generate Fibre
HiPerClockS™ _{Channel reference clock frequencies and is}
a member of the HiPerClocks^TM family of high
performance clock solutions from ICS. Using
a 26.5625MHz 18pF parallel resonant crystal, the following
frequencies can be generated based on the 2 frequency
select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz.
The ICS848004I uses ICS’ 3^rd generation low phase
noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel
jitter requirements. The ICS848004I is packaged in a
small 24-pin TSSOP package.
FEATURES
• Four SSTL_2 differential clock output pairs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.80ps (typical)
• SSTL operating voltage supply ranges:
V = 3.0V to 3.6V, V = 3.0V to 3.6V
DD
DDO
V_DD = 2.3V to 3.6V, V_DDO = 2.3V to 2.7V
V_DD = 2.3V to 3.6V, V_DDO = 1.7V to 1.9V
• -40°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
Input
Frequency
(MHz)
26.5625
F_SEL1
Inputs
F_SEL0
M Divider
Value
N Divider
Value
M/N Divider
Value
Output
Frequency
(MHz)
0
0
24
3
8
212.5
26.5625
0
1
24
4
6
159.375
26.5625
1
0
24
6
4
106.25
26.5625
1
1
24
12
2
53.125
26.04166
0
1
24
4
6
156.25
23.4375
0
0
24
3
8
187.5
BLOCK DIAGRAM
F_SEL[1:0] ^Pulldown
nPLL_SEL ^Pulldown
TEST_CLK ^Pulldown
1
26.5625MHz
XTAL_IN
OSC
0
XTAL_OUT
nXTAL_SEL ^Pulldown
2
Phase
Detector
1
VCO
637.5MHz
(w/26.5625MHz
0
Reference)
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
M = 24 (fixed)
PIN ASSIGNMENT
nQ1 1
Q1 2
VDDo 3
Q0 4
nQ0 ⁵
MR ⁶
nPLL_SEL ⁷
nc ⁸
VDDA ⁹
F_SEL0 ¹⁰
VDD ¹¹
F_SEL1 ¹²
24 nQ2
23 Q2
2 2 VDDO
21 Q3
20 nQ3
19 _GND
18 nc
17 nXTAL_SEL
16 _{TEST_CLK}
15 _GND
14 _{XTAL_IN}
13 _{XTAL_OUT}
ICS848004I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Q0
Top View
nQ0
Q1
nQ1
Q2
nQ2
Q3
MR ^Pulldown
nQ3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
848004AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 18, 2005
1