ICS627-01 Datasheet, PDF (2/4 Pages) Integrated Circuit Systems – HDTV Set-Top Clock Source

PRELIMINARY INFORMATION
ICS627-01
HDTV Set-Top Clock Source
Pin Assignment
SA2 1
X2 2
X1 3
VDD 4
VDD 5
CLKIN 6
VDD 7
VDD 8
VDD 9
GND 10
GND 11
CLKC/2 12
CLKC 13
CLKB ¹⁴
28 SA2
27 SA0
26 SA0
25 REFOUT
24 GND
23 CLKA
22 VDD
21 GND
20 GND
19 GND
18 GND
17 SB
16 SA1
15 SA1
CLKA/CLKC Select Table (MHz)
SA2 SA1 SA0 Input
CLKA
0 0 0 27.0
108.0
0 0 1 27.0 74.175824*
0 1 0 27.0
54.0
0 1 1 27.0
74.25*
1 0 0 TEST
1 0 1 27.0
74.175824
1 1 0 TEST
1 1 1 27.0
74.250
CLKC
54.0
TEST
54.0
54.0
54.0
54.0
CLKC/2
27.0
TEST
27.0
27.0
27.0
27.0
* These selections are recommended for the lowest jitter
CLKB Select Table (MHz)
SB CLKIN
CLKB
0
13.5
27.027
1 27 - 54 27.027 - 54.054
Multiplier
2002/1000
1001/1000
0 = connect directly to GND
1 = connect directl to VDD
Pin Descriptions
Number
1, 28
2
3
4, 5, 7-9, 22
6
10, 11, 18, 19
12
13
14
15, 16
17
20, 21, 24
23
25
26, 27
Name
SA2
X2
X1/ICLK
VDD
CLKIN
GND
CLKC/2
CLKC
CLKB
SA1
SB
GND
CLKA
REFOUT
SA0
Type
I
XO
XI
P
CI
P
O
O
O
I
I
P
O
O
I
Description
Pins 1, 28 should be connected together. Selects CLKA and CLKC frequencies. Internal p-u.
Connect to a fundamental 27.0 MHz crystal or leave unconnected for clock.
Connect to a fundamental 27.0 MHz crystal or clock input.
Connect to 3.3V.
Clock input to produce 1001/1000 or 2(1001/1000) at CLKB. See table above.
Connect to ground.
C Clock output divided-by-2. See table above.
C Clock output. See above table.
B Clock output. See above table.
Pins 15, 16 should be connected together. Selects CLKA and CLKC frequencies. Internal p-u.
B Clock Select. Selects CLKB frequency. See above table. Internal pull-up.
Connect to ground.
A Clock output. See above table.
27 MHz Reference Output.
Pins 26, 27 should be connected together. Selects CLKA and CLKC frequencies. Internal p-u.
Key: I = Input; O = output; P = power supply connection; XI, XO = crystal connections; CI = clock input
MDS 627-01 B
2
Revision 051600
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