ICS601-02 Datasheet, PDF (2/5 Pages) Integrated Circuit Systems – Low Phase Noise Clock Multiplier

ICS601-02
Low Phase Noise Clock Multiplier
Pin Assignment
CLK 1
VDDP ₂
VDD 3
VDD 4
VDD 5
X2 6
S1 7
X1/ICLK 8
16 GND
15 GND
14 GND
13 GND
12 OE
11 S0
10 S3
9 S2
Pin Descriptions
Multiplier Select Table
S3 S2 S1 S0 CLK (see note 2 on following page)
0000
Input x4/3
0001
Input x4
0010
Input x25/4
0011
Input x3
0100
Input x7.5
0101
Input x5
0110
Input x6
0111
Input x8
1000
Input x8/3
1001
Input x8
1010
Input x12.5
1011
Input x6
1100
Input x15
1101
Input x10
1110
Input x12
1111
Input x16
0=connect directly to ground
1=connect directly to VDD
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
CLK
VDDP
VDD
VDD
VDD
X2
S1
X1/ICLK
S2
S3
S0
OE
GND
GND
GND
GND
Type
O
P
P
P
P
XO
I
XI
I
I
I
I
P
P
P
P
Description
Clock output from VCO. Output frequency equals the input frequency times multiplier.
Supply pin for CLK output buffer. Sets output clock amplitude. Connect to 2.5V or 3.3V
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.
Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.
Crystal connection. Connect to a 10-27 MHz fundamental parallel mode crystal, or clock.
Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.
Output Enable. Tri-states the output clock when low. Internal pull-up.
Connect to ground.
Connect to ground.
Connect to ground.
Connect to ground.
Key: I = Input with internal pull-up resistor; O = output; P = power supply connection; XI, X2 = crystal connections.
MDS 601-02 D
2
Revision 111204
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