ICS601-02 Datasheet, PDF (1/5 Pages) Integrated Circuit Systems – Low Phase Noise Clock Multiplier

ICS601-02
Low Phase Noise Clock Multiplier
Description
Features
The ICS601-02 is a low cost, low phase noise, high
performance clock synthesizer for any application that
requires low phase noise and low jitter. The ICS601 is
ICS’ lowest phase noise multiplier. Using ICS’ patented
analog and digital Phase Locked Loop (PLL)
techniques, the chip accepts a 10-27 MHz crystal or
clock input, and produces output clocks up to 170
MHz at 3.3 V. A separate supply pin is provided so that
the output can be 2.5 V.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
timing, use the ICS670-01.
• Packaged in 16 pin SOIC (Pb free)
• Uses fundamental 10 - 27 MHz crystal, or clock
• Patented PLL with the lowest phase noise
• Output clocks up to 170 MHz at 3.3 V
• Low phase noise: -132 dBc/Hz at 10 kHz
• Output Enable function tri states outputs
• Low jitter - 18 ps one sigma
• Full swing CMOS outputs with 25 mA drive
capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• Industrial temperature
• 3.3 V or 5 V core VDD. Output clock can operate
down to 2.5 V
Block Diagram
VDD
VDDP
Reference
Divide
X1/ICLK
X2
Crystal
Oscillator
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
ROM Based
Multipliers
VCO
Divide
Output
Buffer
CLK
Optional crystal
capacitors
GND
S3 S2 S1 S0
OE
needed
for accurate
tuning
(not shown)
MDS 601-02 D
1
Revision 111204
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • [phone]tel • www.icst.com