ICS952011 Datasheet, PDF (16/25 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4 processor

Integrated
Circuit
Systems, Inc.
ICS952011
I²C Table: Output Divider Control Register
Byte 15
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
SDDiv3
SDDiv2
SDDiv1
SDDiv0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
Control
Function
SD divider ratio can be
configured via these 4
bits individually.
CPU divider ratio can be
configured via these 4
bits individually.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
See Table 4: Divider Ratio
Combination Table
See Table 4: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
Table 4: CPU, SDR Divider Ratio Combination Table
Divider (3:2)
Bit
00
01
10
11
MSB
1
2
4
8
00
0000
2
0100
4
1000
8
1100
16
01
0001
3
0101
6
1001
12
1101
24
10
0010
5
0110
10
1010
20
1110
40
11
0011
7
0111
14
1011
28
1111
56
LSB
Address
Div
Address
Div
Address
Div
Address
Div
I²C Table: Output Divider Control Register
Byte 16
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I²C Table: Output Divider Control Register
Byte 17
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
SDINV
CPUINV
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
SD Phase Invert
CPU Phase Invert
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
0
-
-
Default
Default
-
-
-
-
1
-
-
Inverse
Inverse
-
-
-
-
PWD
X
X
X
X
X
X
X
X
0721A—07/29/03
16