ICS952011 Datasheet, PDF (14/25 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4 processor

Integrated
Circuit
Systems, Inc.
I²C Table: Output Control Register
Byte 7
Pin #
Name
Bit 7
15
Bit 6
14
Bit 5
23
Bit 4
22
Bit 3
21
Bit 2
20
Bit 1
17
Bit 0
16
PCICLK_F1
PCICLK_F0
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Control
Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
ICS952011
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
I²C Table: Byte Count Register
Byte 8
Pin #
Name
Control
Function
Type
0
Bit 7
-
BC7
RW
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
BC6
RW
-
BC5
Writing to this register will
RW
-
BC4
configure how many
RW
-
BC3
bytes will be read back,
RW
-
BC2
default is 0F = 15 bytes.
RW
-
Bit 1
-
BC1
RW
-
Bit 0
-
BC0
RW
-
1
PWD
-
0
-
0
-
0
-
0
-
1
-
1
-
1
-
1
I²C Table: Watchdog Timer Register
Byte 9
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
Control
Function
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is 16 X 290ms
=4.64 seconds
Type
RW
RW
RW
RW
RW
RW
RW
RW
I²C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control
Function
Bit 7
-
M/NEN
M/N Programming
Enable
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WDEN
Reserved
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Watchdog Enable
Reserved
Writing to these bit will
configure the safe
frequency as Byte4bit 2,
(7:4)
Type
RW
R
RW
RW
RW
RW
RW
RW
0
1
PWD
-
-
0
-
-
0
-
-
0
-
-
1
-
-
0
-
-
0
-
-
0
-
-
0
0
Disable
Disable
-
-
-
-
-
-
1
Enable
Enable
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
1
0721A—07/29/03
14