ICS952011 Datasheet, PDF (10/25 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4 processor

Integrated
Circuit
Systems, Inc.
ICS952011
I²C Table: Function Control Register
Byte 0
Pin #
Name
Bit 7
-
PDEN
Bit 6
-
AZCLKFS
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WDS_EN
PCICLK6
AZCLKFS
Reserved
AEN1
AEN0
Control
Function
PD# Enable
Async Zclk Freq Select in
N-programming (Mode
01, see table 3)
WD Soft Enable
Output Control
Async Zclk Freq Select
(Mode 10 & 11, see table
3)
Reserved
Zclk/Agp/Pci Freq
Source Select Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
1
Enable
PWD
1
66.6MHz
133.3MHz
1
Disable
Enable
1
Disable
Enable
1
66MHz
132MHz
1
-
1
See Table 3 : ZCLK, AGP &
0
PCI Frequency Source
Decode Table
0
Table 3: ZCLK Frequency Source Decode Table
Byte0 Bit1 Byte0 Bit0
ZCLK & AGP & PCI
0
0
See Table 1, QuadRom Frequency Table
0
1
N-Programming for ZCLK/AGP/PCI
1
0
See Table 1 for AGP/PCI, B0b3 for ZCLK freq
1
1
N-Prog for AGP/PCI, B0b3 for ZCLK freq
I²C Table: Async N-Programming Frequency Select Register
Byte 1
Pin #
Name
Control
Function
Type
0
Bit 7
-
N PLL3 Div7
RW
-
Bit 6
-
N PLL3 Div6
The decimal
RW
-
Bit 5
-
N PLL3 Div5
representation of N PLL2
RW
-
Bit 4
-
N PLL3 Div4
Div (7:0) + 8 is equal to
RW
-
Bit 3
-
N PLL3 Div3
VCO divider value for
RW
-
Bit 2
-
N PLL3 Div2
PLL2. Default at power
RW
-
Bit 1
-
N PLL3 Div1
up = 66.67MHz
RW
-
Bit 0
-
N PLL3 Div0
RW
-
I²C Table: Reserved Register
Byte 2
Pin #
Bit 7
-
Bit 6
-
Bit 5
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
1
PWD
-
0
-
1
-
0
-
0
-
0
-
1
-
1
-
1
1
PWD
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
0721A—07/29/03
10