ICS1572 Datasheet, PDF (15/19 Pages) Integrated Circuit Systems – User Programmable Differential Output Graphics Clock Generator

ICS1572
AC Characteristics
SYMBOL
Fvco
Fxtal
Cpar
Fload
Txhi
Txlo
Thigh
Jclk
Tlock
Idd
Iddo
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PARAMETER
MIN
TYP
VCO Frequency (see Note 1)
20
Crystal Frequency
5
Crystal Oscillator Loading Capacitance
20
LOAD Frequency
XTAL1 High Time (when driven externally)
8
XTAL1 Low TIme (when driven externally)
8
Differential Clock Output Duty Cycle
(see Note 2)
Differential Clock Output Cumulative
Jitter (see Note 3)
PLL Acquire Time (to within 1%)
45
<0.06
500
VDD Supply Current
15
VDDO Supply Current (excluding CLK+/-
20
termination)
DIGITAL INPUTS - ICS1572-101
Address Setup Time
10
Address Hold Time
10
Data Setup Time
10
Data Hold Time
10
STROBE Pulse Width (Thi or Tlo)
20
DIGITAL OUTPUTS - ICS1572-301
DATA/HOLD~Setup Time
10
DATA/HOLD~Hold Time
10
DATCLK Pulse Width (Thi or Tlo)
20
PIPELINE DELAY RESET
Reset Activation Time
Reset Duration
4*Tload
Restart Delay
Restart Matching
-1*Tclk
DIGITAL OUTPUTS
CLK+/CLK- Clock Rate
LOAD To LD/N2 Skew (Shift Clock Mode)
-2
0
MAX
160
20
80
55
t.b.d.
t.b.d.
UNITS
MHz
MHz
pF
MHz
ns
ns
%
pixel
µs
mA
mA
2*Tclk
2*Tload
+1.5*Tclk
180
+2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
Note 1: Use of the post-divider is required for frequencies lower than 20 MHz on CLK+ & CLK- outputs. Use of the post-divider
is recommended for output frequencies lower than 65 MHz.
Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-.
Note 3: Cumulative jitter is defined as the maximum error (in the time domain) of any CLK edge, at any point in time, compared
with the equivalent edge generated by an ideal frequency source.
ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in
virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register
programming.
15