ICS1572 Datasheet, PDF (13/19 Pages) Integrated Circuit Systems – User Programmable Differential Output Graphics Clock Generator

ICS1572
Pin Descriptions - ICS1572-101
PIN#
13
12
8
3
4
2
19
18
17
9
5
16
15
14
6,7
1,10,11,20
NAME
CLK+
CLK−
LOAD
XTAL1
XTAL2
AD0
AD1
AD2
AD3
LD/N2
STROBE
VDD
VDDO
IPRG
VSS
NC
DESCRIPTION
Clock out (non-inverted)
Clock out (inverted)
Load output. This output is normally at the CLK frequency divided by N1.
Quartz crystal connection 1/external reference frequency input
Quartz crystal connection 2
Address/Data Bit 0 (LSB)
Address/Data Bit 1
Address/Data Bit 2
Address/Data Bit 3 (MSB)
Divided LOAD output. See text.
Control for address/data latch
PLL system power (+5V. See application diagram.)
Output stage power (+5V)
Output stage current set
Device ground. Both pins must be connected to the same ground potential.
Not connected
Pin Descriptions - ICS1572-301
PIN#
13
12
8
3
4
5
19
18
17
9
2
16
15
14
6,7
1,10,11,20
NAME
CLK+
CLK−
LOAD
XTAL1
XTAL2
DATCLK
DATA
HOLD~
BLANK
LD/N2
EXTFBK
VDD
VDDO
IPRG
VSS
NC
DESCRIPTION
Clock out (non-inverted)
Clock out (inverted)
Load output. This output is normally at the CLK frequency divided by N1.
Quartz crystal connection 1/external reference frequency input
Quartz crystal connection 2
Data Clock (Input)
Serial Register Data (Input)
HOLD (Input)
Blanking (Input). See Text.
Divided LOAD output/shift clock. See text.
External feedback connection for PLL (input). See text.
PLL system power (+5V. See application diagram.)
Output stage power (+5V)
Output stage current set
Device ground. Both pins must be connected.
Not connected
13