ICS1572 Datasheet, PDF (10/19 Pages) Integrated Circuit Systems – User Programmable Differential Output Graphics Clock Generator

ICS1572
BIT(S)
13-14
15
16
17-24
28
25-27
BIT REF.
S[0]..S[1]
AUX_CLK
AUX_N1
N2[0]..N2[7]
N2[8]
V[0]..V[2]
DESCRIPTION
PLL post-scaler/test mode select bits.
S[1] S[0]
DESCRIPTION
0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider drives
the LOAD output which, in turn, drives the N2 divider.
0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
1 1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD
output which, in turn, drives the N2 divider.
When in the AUXEN clock mode, this bit controls the differential outputs.
When in the AUXEN clock mode, this bit controls the N1 output (and
consequently the N2 output according to its programming).

 Sets the modulus of the N2 divider. The input of the N2 divider is the
 output of the N1 divider in all clock modes except AUXEN.
Sets the gain of VCO.
29-30
31
32
P[0]..P[1]
RESERVED
P[2]
V[2]
V[1]
V[0]
VCO GAIN
(MHz/VOLT)
1
0
0
30
1
0
1
45
1
1
0
60
1
1
1
80
Sets the gain of the phase detector according to this table.
P[1]
P[0]
GAIN (uA/radian)
0
0
0.05
0
1
0.15
1
0
0.5
1
1
1.5
Set to zero.
Phase detector tuning bit. Should normally be set to one.
10