ICS950223 Datasheet, PDF (14/24 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950223
I²C Table: Output Divider Control Register
Byte 15
Pin #
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
CPU Div3
CPU Div2
CPU Div1
CPU Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
CPUCLK2 divider ratio
can be configured via
these 4 bits individually.
CPUCLK [1:0] divider
ratio can be configured
via these 4 bits
individually.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
See Table 3: Divider Ratio
Combination Table
See Table 3: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
Table 3: CPU, AGP and PCI Divider Ratio Combination Table
Bit
00
Divider (3:2)
01
10
11
MSB
1
2
4
8
00
0
2
100
4
1000
8
1100
16
01
1
3
101
6
1001
12
1101
24
10
10
11
11
5
110
10
1010
20
1110
40
7
111
14
1011
28
1111
56
LSB
Address
Div
Address
Div
Address
Div
Address
Div
I²C Table: Output Divider Control Register
Byte 16
Pin #
Name
Control Function
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
3V66 Div3
3V66 Div2
3V66 Div1
3V66 Div0
3V66 Div3
3V66 Div2
3V66 Div1
3V66 Div0
3V66 [3:2] divider ratio
can be configured via
these 4 bits individually
3V66 [1:0] divider ratio
can be configured via
these 4 bits individually.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
See Table 3: Divider Ratio
Combination Table
See Table 3: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
I²C Table: Output Divider Control Register
Byte 17
Pin #
Name
Control Function
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
3V66INV
3V66INV
CPUINV
CPUINV
PCI Div3
PCI Div2
PCI Div1
PCI Div0
3V66[3:2] Phase Invert
3V66[1:0] Phase Invert
CPU Phase Invert
CPU Phase Invert
PCI divider ratio can
be configured via these
4 bits individually.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Default
Default
Default
Default
1
Inverse
Inverse
Inverse
Inverse
See Table 3: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
0496C—05/06/05
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