ICS950223 Datasheet, PDF (11/24 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950223
I²C Table: Output Control Register
Byte 3
Pin #
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
23
24_48MHz
Output Control
22
48MHz
Output Control
-
GR_EN
Geashift Reset Enable
-
24_48 FS Source
24_48 Frequency H/W
/ IIC Select
-
FS 24_48
Sel24_48
8
PCICLK2
Output Control
7
PCICLK1
Output Control
6
PCICLK0
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
ON
Latch Inputs
24MHz
Disable
Disable
Disable
1
Enable
Enable
OFF
IIC
48MHz
Enable
Enable
Enable
PWD
1
1
0
0
0
1
1
1
I²C Table: Output Control Register
Byte 4
Pin #
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
66_48 FS Source ^{66_48 Frequency H/W}
/ IIC Select
-
FS 66_48#
Sel66_48#
31
3V66_0
Output Control
30
3V66_1
Output Control
48
REF0
Output Control
1
REF1
Output Control
27
3V66_3
Output Control
28
3V66_2
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Latch Inputs
48MHz
Disable
Disable
Disable
Disable
Disable
Disable
IIC
66.66MHz
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
0
1
1
1
1
1
1
I²C Table: 3V66 & PCICLK Asynchronous Frequency Control Register
Byte 5
Pin #
Name
Control Function
Type
0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
N PLL2 Div0
RW
-
N PLL2 Div1
RW
-
N PLL2 Div2
The decimal
RW
-
N PLL2 Div3
representation of N
PLL2 Div (0:7) + 8 is
RW
-
N PLL2 Div4
equal to VCO divider
RW
-
N PLL2 Div5
value for PLL2.
RW
-
N PLL2 Div6
RW
-
N PLL2 Div7
RW
-
1
PWD
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
I²C Table: Read Back Register
Byte 6
Pin #
Name
Control Function
Type
0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WDHRB
WD Hard Alarm Status
Read back
R
-
SEL48_24RB Sel48_24# Read Back
R
-
SEL66_48RB Sel66_48# Read Back
R
FS4RB
FS4 Read back
R
-
FS3RB
FS3 Read back
R
-
FS2RB
FS2 Read back
R
-
FS1RB
FS1 Read back
R
-
FS0RB
FS0 Read back
R
-
0496C—05/06/05
11
1
PWD
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X