ICS950223 Datasheet, PDF (1/24 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950223
Programmable Timing Control Hub™ for P4™
Recommended Application:
Pin Configuration
Brookdale and Brookdale-G chipset with P4 processor.
Output Features:
• 3 - Pairs of differential CPU clocks
(differential current mode)
*MULTSEL1/REF1 1
VDDREF 2
X1 3
X2 4
48 REF0/MULTSEL0**
47 GNDREF
46 VDDCPU
45 CPUCLKT2
• 3 - 3V66 @ 3.3V
• 10 - PCI @ 3.3V
• 1 - 48MHz @ 3.3V fixed
GND 5
*FS2/PCICLK0 6
*FS3/PCICLK1 7
**SEL48_24#/PCICLK2 8
44 CPUCLKC2
43 GNDCPU
42 PD#*
41 CPUCLKT0
• 2 - REF @ 3.3V, 14.318MHz
• 1 - 48_66MHz selectable @ 3.3V fixed
• 1 - 24_48MHz selectable @ 3.3V
VDDPCI 9
*FS4/PCICLK3 10
PCICLK4 11
PCICLK5 12
40 CPUCLKC0
39 VDDCPU
38 CPUCLKT1
37 CPUCLKC1
GND 13
36 GNDCPU
PCICLK6 14
35 IREF
Features/Benefits:
• QuadRom^TM frequency selection.
• Programmable output frequency.
• Programmable asynchronous 3V66 & PCI frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
PCICLK7 15
PCICLK8 16
PCICLK9 17
VDDPCI 18
Vttpwr_GD# 19
RESET# 20
GND 21
~_{*FS0/48MHz 22}
34 AVDD
33 GND
32 VDD3V66
31 3V66_0
30 3V66_1
29 GND
28 3V66_2
27 3V66_3_48MHz/Sel66_48#**
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
*FS1/24_48MHz 23
26 SCLK
AVDD48 24
25 SDATA
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
• Programmable watchdog safe frequency.
~ _{This output has 2X drive strength}
• Support I²C Index read/write and block read/write
operations.
• Uses external 14.318MHz reference input.
Frequency Table
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
FS4 FS3 FS2 FS1 FS0 MHz
3V66
MHz
PCI
MHz
0
0
0
0
0 102.00 68.00 34.00
Key Specifications:
• CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
0
0
0
0
1 105.00 70.00 35.00
0
0
0
1
0 108.00 72.00 36.00
0
0
0
1
1 111.00 74.00 37.00
0
0
1
0
0 114.00 76.00 38.00
0
0
1
0
1 117.00 78.00 39.00
0
0
1
1
0 120.00 80.00 40.00
Block Diagram
0
0
1
1
1 123.00 82.00 41.00
0
1
0
0
0 126.00 72.00 36.00
0
1
0
0
1 130.00 74.29 37.14
PLL2
X1
XTAL
/2
X2
OSC
48MHz
24_48MHz
REF (1:0)
0
1
0
1
0 136.00 68.00 34.00
0
1
0
1
1 140.00 70.00 35.00
0
1
1
0
0 144.00 72.00 36.00
0
1
1
0
1 148.00 74.00 37.00
0
1
1
1
0 152.00 76.00 38.00
3V66
DIVDER
3V66_48MHz
0
1
1
1
1 156.00 78.00 39.00
1
0
0
0
0 160.00 80.00 40.00
PD#
MULTSEL(1:0)
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
SEL 48_24#
SEL 66_48#
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
CPU
DIVDER
PCI
DIVDER
3V66
DIVDER
3 ^{CPUCLKT (2:0)}
3 ^{CPUCLKC (2:0)}
PCICLK (9:0)
10
3V66 (2:0)
4
RESET#
I REF
1
0
0
0
1 164.00 82.00 41.00
1
0
0
1
0 166.60 66.64 33.32
1
0
0
1
1 170.00 68.00 34.00
1
0
1
0
0 175.00 70.00 35.00
1
0
1
0
1 180.00 72.00 36.00
1
0
1
1
0 185.00 74.00 37.00
1
0
1
1
1 190.00 76.00 38.00
1
1
0
0
0 66.80 66.80 33.40
1
1
0
0
1 100.20 66.80 33.40
1
1
0
1
0 133.60 66.80 33.40
1
1
0
1
1 200.40 66.80 33.40
1
1
1
0
0 66.67 66.67 33.34
1
1
1
0
1 100.00 66.67 33.33
0496C—05/06/05
1
1
1
1
0 200.00 66.67 33.33
1
1
1
1
1 133.33 66.67 33.33