ICS8344I Datasheet, PDF (1/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8344I is a low voltage, low skew fanout
,&6
buffer and a member of the HiPerClockS™
HiPerClockS™ _{family of High Performance Clock Solutions from}
ICS. The ICS8344I has two selectable clock in-
puts. The CLK0, nCLK0 and CLK1, nCLK1 pairs
can accept most standard differential input levels. The
ICS8344I is designed to translate any differential signal lev-
els to LVCMOS levels. The low impedance LVCMOS outputs
are designed to drive 50Ω series or parallel terminated trans-
mission lines. The effective fanout can be increased to 48 by
utilizing the ability of the outputs to drive two series termi-
nated lines. Redundant clock applications can make use of
the dual clock input. The dual clock inputs also facilitate board
level testing. ICS8344I is characterized at full 3.3V, full 2.5V
and mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS8344I ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
FEATURES
• 24 LVCMOS outputs, 7Ω typical output impedance
• 2 selectable differential clock input pairs for redundant clock
applications
• CLKx, nCLKx pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency up to 100MHz
• Translates any single-ended input signal to LVCMOS with
resistor bias on nCLK input
• Multiple output enable pins for disabling unused outputs in
reduced fanout applications
• Output skew: 275ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Bank skew: 150ps (maximum)
• 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
CLK_SEL
CLK0
nCLK0
0
CLK1
1
nCLK1
OE1
OE2
OE3
8344BYI
PIN ASSIGNMENT
Q0 - Q7
Q8 - Q15
Q16 - Q23
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
7
ICS8344I
31
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
Q7
Q6
VDDO
GND
Q5
Q4
Q3
Q2
VDDO
GND
Q1
Q0
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 9, 2001