IC62LV1024AL Datasheet, PDF (9/11 Pages) Integrated Circuit Solution Inc – 128K x 8 Ultra Low Power and Low VCC SRAM

IC62LV1024AL
IC62LV1024ALL
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)^(1,2)
ADDRESS
CE1
CE2
WE
DOUT
DIN
tWC
tSA
tSCE1
tHA
tSCE2
tAW
tPWE⁽⁴⁾
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
Test Condition
Min. Max.
Unit
VDR
Vcc for Data Retention
See Data Retention Waveform
2.0 3.3
V
IDR
Data Retention Current
Vcc = 2.0V, CE1 ≥ Vcc – 0.2V Com. (-L) — 30
µA
Com. (-LL) — 5
µA
Ind. (-L) — 50
µA
Ind. (-LL) — 10
µA
tSDR
Data Retention Setup Time See Data Retention Waveform
0—
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC —
ns
DATA RETENTION WAVEFORM (CE1 Controlled)
V_CC
3.0V
t_SDR
Data Retention Mode
t_RDR
2.2V
V_DR
CE1
GND
CE1 ≥ V_CC - 0.2V
Integrated Circuit Solution Inc.
9
LPSR017-0A 09/13/2001