IC61C1024 Datasheet, PDF (9/11 Pages) Integrated Circuit Solution Inc – 128K x 8 HIGH-SPEED CMOS STATIC RAM

IC61C1024
IC61C1024L
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) ^{(1 )}
ADDRESS
CE
WE
DOUT
DIN
t WC
VALID ADDRESS
t SA
t SCE
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) ^(1,2)
ADDRESS
OE
t WC
VALID ADDRESS
t HA
CE ^LOW
WE
DOUT
t SA
DATA UNDEFINED
t AW
t PWE1
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DIN
DATAIN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Circuit Solution Inc.
9
AHSR008-0B 10/18/2001