IC61C1024 Datasheet, PDF (8/11 Pages) Integrated Circuit Solution Inc – 128K x 8 HIGH-SPEED CMOS STATIC RAM

IC61C1024
IC61C1024L
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range, Standard and Low
Power)
Symbol Parameter
-12 ns⁽³⁾
Min. Max.
-15 ns
Min. Max.
-20 ns
Min. Max.
-25 ns
Min. Max. Unit
tWC Write Cycle Time
tSCE1 CE1 to Write End
12 —
10 —
15 —
12 —
20 —
15 —
25 —
ns
20 —
ns
tSCE2 CE2 to Write End
10 —
12 —
15 —
20 —
ns
tAW Address Setup Time to Write End 10 —
12 —
15 —
20 —
ns
tHA Address Hold from Write End
0—
0—
0—
0—
ns
tSA Address Setup Time
tPWE⁽⁴⁾ WE Pulse Width
0—
10 —
0—
10 —
0—
12 —
0—
ns
15 —
ns
tSD Data Setup to Write End
7—
8—
10 —
12 —
ns
tHD
tHZWE⁽⁵⁾
tLZWE⁽⁵⁾
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0—
—7
2—
0—
—7
2—
0—
— 10
2—
0—
ns
— 12
ns
2—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. -12 ns device for IC61C1024 only.
4. Tested with OE HIGH.
5. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001