IC41C8512 Datasheet, PDF (9/21 Pages) Integrated Circuit Solution Inc – 512K x 8 bit Dynamic RAM with EDO Page Mode

IC41C8512
IC41LV8512
AC CHARACTERISTICS (Continued)^{(1,2,3,4,5,6)}
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tACH
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tCOH
tOFF
tWHZ
tCLCH
tCSR
tCHR
tORD
tREF
tT
Parameter
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODIFY-WRITE cycle⁽¹⁸⁾
Data-In Setup Time^{(15, 22)}
Data-In Hold Time^{(15, 22)}
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle⁽¹⁴⁾
CAS to WE Delay Time^{(14, 20)}
Column-Address to WE Delay Time⁽¹⁴⁾
EDO Page Mode READ or WRITE
Cycle Time⁽²⁴⁾
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge⁽¹⁵⁾
EDO Page Mode READ-WRITE
Cycle Time⁽²⁴⁾
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS^{(13,15,19, 29)}
Output Disable Delay from WE
Last CAS going LOW to First CAS
returning HIGH⁽²³⁾
CAS Setup Time (CBR REFRESH)^{(30, 20)}
CAS Hold Time (CBR REFRESH)^{(30, 21)}
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Refresh Period (512 Cycles)
Transition Time (Rise or Fall)^{(2, 3)}
35
Min. Max.
15 —
8—
0—
6—
80 —
45 —
25 —
30 —
12 —
35 100K
— 21
40 —
5—
3 15
3 15
10 —
8—
8—
0—
—8
1 50
-50
Min. Max.
15 —
10 —
0—
8—
125 —
70 —
34 —
42 —
20 —
50 100K
— 27
47 —
5—
3 15
3 15
10 —
10 —
10 —
0—
8—
1 50
-60
Min. Max.
15 —
15 —
0—
10 —
140 —
80 —
36 —
49 —
25 —
50 100K
— 34
56 —
5—
3 15
3 15
10 —
10 —
10 —
0—
8—
1 50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Circuit Solution Inc.
9
DR029-0A 09/28/2001