IC41C8512 Datasheet, PDF (7/21 Pages) Integrated Circuit Solution Inc – 512K x 8 bit Dynamic RAM with EDO Page Mode

IC41C8512
IC41LV8512
ELECTRICAL CHARACTERISTICS⁽¹⁾
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
IIL
Input Leakage Current
IIO
Output Leakage Current
VOH
Output High Voltage Level
VOL
Output Low Voltage Level
ICC1
Standby Current: TTL
Test Condition
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
IOH = –2.5 mA
IOL =+2.1mA
RAS, CAS ≥ VIH
ICC2
Standby Current: CMOS
RAS, CAS ≥ VCC – 0.2V
ICC3
Operating Current:
RAS, CAS,
Random Read/Write^(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
ICC4
Operating Current:
RAS = VIL, CAS,
EDO Page Mode^(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
ICC5
Refresh Current:
RAS-Only^(2,3)
RAS Cycling, CAS ≥ VIH
tRC = tRC (min.)
Average Power Supply Current
ICC6
Refresh Current:
RAS, CAS Cycling
CBR^(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
Speed Min. Max. Unit
–10 10 µA
–10 10 µA
2.4 —
V
— 0.4
V
5V —
3.3V —
2 mA
0.5
5V —
3.3V —
1 mA
0.5
-35 — 120 mA
-50 — 110
-60 — 100
-35 — 100 mA
-50 — 90
-60 — 80
-35 — 120 mA
-50 — 110
-60 — 100
-35 — 120 mA
-50 — 110
-60 — 100
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
7
DR029-0A 09/28/2001