IC41C16100A Datasheet, PDF (9/21 Pages) Integrated Circuit Solution Inc – 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
AC CHARACTERISTICS (Continued)^{(1,2,3,4,5,6)}
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tCOH
tOFF
tWHZ
tCSR
tCHR
tRPC
tORD
tREF
tT
Parameter
OE Hold Time from WE during
READ-MODIFY-WRITE cycle⁽¹⁸⁾
Data-In Setup Time^{(15, 22)}
Data-In Hold Time^{(15, 22)}
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle⁽¹⁴⁾
CAS to WE Delay Time^{(14, 20)}
Column-Address to WE Delay Time⁽¹⁴⁾
EDO Page Mode READ or WRITE
Cycle Time⁽²⁴⁾
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge⁽¹⁵⁾
EDO Page Mode READ-WRITE
Cycle Time⁽²⁴⁾
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS^{(13,15,19, 29)}
Output Disable Delay from WE
CAS Setup Time (CBR REFRESH)^{(30, 20)}
CAS Hold Time (CBR REFRESH)^{(30, 21)}
RAS to CAS Precharge Time
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Auto Refresh Period (1,024 Cycles)
Transition Time (Rise or Fall)^{(2, 3)}
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
-50
Min. Max.
8
—
-60
Min. Max.
10 —
Units
ns
0
—
0
— ns
8
— 10 — ns
108 — 133 — ns
64 — 77 — ns
26 — 32 — ns
39 — 47 — ns
20 — 25 — ns
50 100K 60 100K ns
— 30 — 35 ns
56 — 68 — ns
5
—
5
— ns
0
12
0
15 ns
3
10
3
10 ns
5
—
5
— ns
8
— 10 — ns
5
—
5
—
ns
0
—
0
— ns
— 16 — 16 ms
1
50
1
50 ns
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Circuit Solution Inc.
9
DR030-0A 09/28/2001