IC62LV256 Datasheet, PDF (8/9 Pages) Integrated Circuit Solution Inc – 32K x 8 Low Power SRAM with 3.3V

IC62LV256
WRITE CYCLE NO. 2 (CE Controlled)^(1,2)
tWC
ADDRESS
tSA
tSCE
tHA
CE
WE
DOUT
DIN
tAW
tPWE
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ VIH.
8
Integrated Circuit Solution Inc.
ALSR007-0A 10/5/2001